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PicLA - a very low cost Logic Analyser
A logic analyser using an 18F2525 PIC microprocessor and a PC. The PIC is used as a hardware capture device which monitors the datalines and records all changes. The buffering, triggering, interpretation and display is handled by a PC program running under Windows.
* User selectable sampling of 4 or 8 channels.
* "Fast Sampling" at 5 MHz / 2 MHz / 1 MHz and 500 kHz giving resolutions of 200nSec to 2 uSec.
* "Normal Sampling" at 500 kHz, 200 kHz, 100 kHz and 50 kHz giving resolutions of 2 uSec to 20 uSec.
* 3584 or 7168 samples can be stored in "Fast sampling" mode (depends on 8 or 4 bit mode)
* In "Normal Sampling" there is no limit to the duration of the trace, the current version supports up to 50 seconds.
* A 256-Event burst buffer is used if the data lines change faster than the data can be transmitted to the PC
* PC Link limits the "average" speed of the logic analyser (The nr. of transitions that can be recorded per second)
* Average limit for 4bit "Normal sampling": 5760 events/sec (115kBit) or 25000 events/sec (500kBit).
* Average limit for 8bit "Normal sampling": 3840 events/sec (115kBit) or 15000 events/sec (500kBit).