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A SPI interface for 6502 processor (probably usable with other 8bit processors too) in the CPLD.

This SPI interface circuit is built in Xilinx XC9572 CPLD. Author provides an ABEL source code as well as JEDEC .jed file.


* CPU bus compatible with 65C02 and 65C816 microprocessors
* 4-byte memory map for host access to registers
* Operates as SPI master
* SCLK derived from PHI2 or an External Clock source
* SCLK has an 6 bit programmable divider – CLK/2 through CLK/128
* SPI Mode 0, 1, 2, 3 supported
* Shifts MSB first
* 8-bit Slave select register with 8 Slave Select outputs
* Direct slave select decoding yields 8 devices, with decoder up to 255 devices
* Programmable interrupt
* Interrupt or polled transmit complete flags

Link: 65SPI

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